Shared buses provide a simple, low-cost means for handling data transfers between various devices or components of an electronic system. Shared buses are used extensively in computer systems and the like. The shared buses may be used to interconnect central processing units (CPUs) to memory systems and to input/output devices. The overall performance of a bus may be determined by the frequency or the speed at which the bus can transmit bits of data, the bandwidth or number of bits the bus can transmit simultaneously and the protocol or set of rules, procedures or conventions relating to formatting and timing of data transmission between two devices of a system. In general, all devices connected to a shared bus rely on the single bus for communicating with each other. The shared bus can establish communications between typically only two devices at any given time. Accordingly, if the shared bus is currently busy transmitting signals between two of the devices, the other devices must wait for their turn to establish communications. This presents latencies in transferring data and slows down the operation of the system. In contrast, there is an increasing demand for faster system operation, higher bandwidths and lower latencies. To meet these demands, more buses can be provided or the bandwidth of the shared bus can be increased by adding more signal lines or conductive traces. Additional lines consume valuable space on printed circuit boards, in the case of an external bus, or silicon area, in the case of on-chip buses. Long sets of parallel lines attached to multiple loads may also present problems, such as impedance mismatches, reflections, cross-talk, noise, nonlinearities, attenuation, distortion, timing problems and the like. Large buses are also inefficient for small data transfers.